The present invention relates to commonly assigned, co-pending U.S. patent application Ser. No. 09/777,202, entitled xe2x80x9cA SYSTEM FOR AND METHOD OF OPERATING A PROGRAMMABLE COLUMN FAIL COUNTER FOR REDUNDANCY ALLOCATION,xe2x80x9d filed Feb. 2, 2001; and commonly assigned, concurrently filed U.S. patent application Ser. No. 09/792,320, entitled xe2x80x9cSYSTEM AND METHOD OF OPERATING A PROGRAMMABLE COLUMN FAIL COUNTER FOR REDUNDANCY ALLOCATION,xe2x80x9d the disclosures of which are hereby incorporated herein by reference.
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having spare memory cells for replacement of defective memory cells which are then programmably accessible.
Modern microprocessors and many Application Specific Integrated Circuits (ASICs) often incorporate large amounts of embedded memory. This memory is typically Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). These Random Access Memories (RAMs) constitute the majority of transistors contained on a chip and can occupy the largest portion of the surface area of a chip, i.e., chip xe2x80x9creal estate.xe2x80x9d Availability and usability of these RAMs becomes a priority to semiconductor manufacturers. Typically semiconductor manufacturers incorporate a test and a repair scheme which tests RAM cells within the chip and replaces defective RAM cells with spare cells included for that purpose. Typically, columns and/or rows of RAM cells are replaced rather than individual RAM cells. Row substitution may be performed by appropriate changes to the address decoder while column substitution may be performed by MUX selection of appropriate bit lines.
Traditionally, semiconductor manufacturers have used bit maps to determine which RAM columns and/or RAM rows need to be replaced with redundant RAM columns or RAM rows. Identification of defective memory cells is a particular problem when embedded on a microprocessor or ASIC device, since external or off-chip access for testing is limited by the number of pins available. Thus, semiconductor manufacturers have incorporated Built In Self Tests (BISTs) and Built In Self Repair (BISRs) to test and replace RAM cells. Special purpose built-in test hardware is described in detail in the commonly assigned and co-pending U.S. patent application Ser. No. 09/183,536, entitled, xe2x80x9cA Flexible And Programmable BIST Engine for On-Chip Memory Array Testing and characterization,xe2x80x9d filed Oct. 30, 1998, the disclosure of which is hereby incorporated herein by reference.
Typically RAM cells are tested for a number of faults which can be classified into two categories, simple faults and linked faults. Simple faults are those which occur independent of other faults but may induce failures in other cells. Linked faults are when two or more simple faults are acting on a single cell (i.e. multiple faults influencing each other). Simple faults can be further divided into Address Decoder Faults (ADFs) and Memory Cell Array Faults (MCAFs). ADFs are only present in the address decoder and result in the unavailability of a cell, the lack of an address to access a cell, an address accessing multiple cells, or a specific cell being accessible with multiple addresses.
MCAFs can be further broken down into single cell faults and faults which occur between memory cells. Single cell faults include Stuck At Faults (SAFs), Stuck Open Faults (SOFs), Transition Faults (TFs), and Data Retention Faults (DRFs). SAF means a specific cell is either xe2x80x9cstuckxe2x80x9d at zero or xe2x80x9cstuckxe2x80x9d at one regardless of the data attempted to be written into the cell. SOF indicates that a memory cell cannot be accessed because of an open line. A TF occurs when a memory cell cannot make a transition from zero to one, or from one to zero. And finally, a DRF occurs when a cell is unable to retain a particular logic value or state for a requisite period of time.
Coupling faults involve two cells. A first cell, the coupling cell, which is the source of the fault, and the second cell, the coupled cell, which is the cell that experiences the fault. These coupling faults can occur either when a transition occurs in the coupling cell or when a specific value is stored in the coupling cell. Transitions in a coupling cell can cause the coupled cell to change from a zero to a one, or vice versa, or can cause a zero or a one to be stored within the coupled cell. Additionally, certain values in coupling cells may bleed through to a coupled cell regardless of the value which should be stored in the coupled cell.
Tests which are applied in parallel to a plurality or group of memory cells, or march tests, consist of a sequence of elements, or xe2x80x9cmarch elements,xe2x80x9d in which a sequence of operations are defined and corresponding data signals are applied to various memory cells, typically one row or column at a time. The overall memory can be divided into memory groups and these tests can occur in parallel across memory groups. The address order determines the order in which the march test is applied to various address locations within a memory group. A march test may contain the following sequence: write zero, read zero, write one, read one, write zero, read zero. This march test would ensure that a zero could be stored in, and read from, a memory cell, that a one can be stored in, and read from, a memory cell, and that the memory cell can transition from a zero to a one, and from one to zero. These march tests are performed on the memory cells during BIST.
Once faulty memory cells have been identified, BISR is used to replace the faulty memory cells with spare memory cells. This typically occurs a column or row at a time or using multiple spare columns or rows to replace a continuous group of columns or rows (e.g., an address space spanning several rows or columns). Semiconductor manufacturers also combine BIST and BISR in accordance with their testing philosophy. BIST could be completed before the BISR has been implemented and not repeated after array reconfiguration in which faulty rows or columns are replaced with spare ones. Thus, if BIST is completed before BISR is performed, the replacement columns and rows are not typically tested during BIST and columns and rows of cells would be included in the operational memory array which have not successfully past BIST.
Alternatively, and more preferably, BIST and BISR can occur alternatively to ensure that each of the memory cells contained in the final (operational) memory array configuration have been thoroughly tested. For instance, one march test may occur during the first pass of BIST and be used to identify faulty memory cells. Once these faulty memory cells have been identified, a first pass of BISR can be used to replace the rows and/or columns of memory which contain these faulty memory cells. Once the first pass of BISR has been completed, the second pass of BIST can be performed which repeats the first BIST pass or which includes additional march tests to ensure that the replacement rows and/or columns, as configured, are operating properly. A second pass of BISR would be performed at the conclusion of the second pass of BIST to replace any newly identified or remaining faulty rows and/or columns. In addition, other march tests can be performed which test for coupling problems between memory cells in the reconfigured array. A BIST, which identifies memory cells with faults, is always followed by BISR, or the memory array is unrepairable and discarded.
Once a row of memory containing a non-operational cell has been identified, its address is typically stored and mapped to a redundant row. This mapping may occur after each row containing a non-operational cell has been identified, or alternatively, testing may be suspended while the row containing the non-operational cell is mapped to a redundant row. Once the mapping is completed, testing of the remaining rows is resumed. For memory addresses which cannot be accessed or stored in a single clock cycle a pipeline may be implemented to allow the access or storage to occur over numerous clock cycles.
A description of memory testing and the use of redundant memory elements is described in detail in the commonly assigned U.S. Pat. No. 6,141,779, issued Oct. 31, 2000, and co-pending U.S. patent application Ser. No. 09/544,516, entitled xe2x80x9cSystem and Method for Providing RAM Redundancy in the Field,xe2x80x9d filed Apr. 6, 2000, the disclosures of which are hereby incorporated herein by reference. Also, U.S. Pat. No. 5,255,227 issued Oct. 19, 1993, to Haeftele; U.S. Pat. No. 5,848,077 issued Dec. 8, 1998, to Kamae et al.; and U.S. Pat. No. 6,000,047 issued Dec. 7, 1999, to Kamae et al., each commonly assigned to the assignee of this patent describe similar correction methods and are hereby incorporated herein by reference.
While BIST and BISR provide enhanced testing facilities and rehabilitation of faulty devices, the additional test and repair circuitry and time used limits incorporation of these tools into the already cramped chip real estate. Accordingly, a need exists for a systematic method and approach to test the memory cells contained within a memory array that will minimize the amount of time spent in BIST and BISR while maximizing the identification of faulty memory cells. A need further exists for the efficient use of redundant memory columns and redundant memory rows in the replacement of faulty memory cells. A further need exists for the identification and replacement of faulty memory cells while minimizing the hardware associated with the BIST, BISR, and surface area of the chip dedicated to BIST and BISR.
The present invention incorporates built-in self test and self repair functionality into a semiconductor memory device in which reconfiguration data used to replace faulty memory is stored at the same time testing to identify other faulty memory cells continues. To avoid access contention conflicts to a content addressable memory used to identify rows or groups of rows having faulty memory cells, the built in test function writes test data to each cell at least twice before reading the stored data. By writing twice before reading, contention problems caused by simultaneous updating of the content addressable memory are avoided. That is, even if the content addressable memory is initially unavailable to process address information used to access a memory cell to be tested, repetition of the write process ensure that the data will be properly stored when the memory again becomes available after being updated.
Thus, according to one aspect of the invention, a method of configuring a memory array to replace faulty memory cells with spare memory cell includes identification of a first address space, the first address space (e.g., row or group of rows) including a faulty memory cell. An attempt to supply data corresponding to a second address space to a content addressable memory and an attempt is made to access at least one memory cell so addressed. During at least some portion of the time that these latter actions occur (i.e., while the CAM is needed to address the memory and test data is to be accessed), data corresponding to the first address space (e.g., the row address of the faulty memory cell) is written into the content addressable memory. An attempt is made to resupply data corresponding to said second address space to the content addressable memory and another attempt is made to access the memory cell addressed. Data is then read from the memory cell and compared with the originally stored test data.
According to another aspect of the invention, a memory includes an array of memory cells including spare memory cells. Memory cell address logic includes a CAM and reconfiguration logic. The CAM stores data representing address spaces corresponding to faulty ones of the memory cells; the memory cell configuration logic is responsive to an output of the CAM for mapping the address spaces corresponding to the faulty memory cells address spaces to respective ones of the spare memory cells. Test logic functions to identify a first address space including a faulty memory cell. The test logic further attempts to supply data (e.g., a partial of full address) corresponding to a second address space to the content addressable memory and attempts to access at least one memory cell in the second address space. The test logic repeats this process by reattempting to supply the data corresponding to the second address space to the content addressable memory and reattempting to access the memory cell addressed. After both access and write operations, the test logic causes data to be read from the memory cell and compares the data as read with the original test data. Memory repair logic is configured to operate in parallel with the test logic while the latter either supplies addressing information or attempts writing test data to the memory, to write data corresponding to the first address space into the content addressable memory (i.e., update the CAM.)
According to another feature of the invention, counting logic functions to count a number of the faulty memory cells in at least one column of the array of memory cells. Alternatively, the test logic may be configured to detect a number of the faulty memory cells in at least one column of the array of memory cells, the number satisfying a threshold criteria. According to another aspect of the invention, a semiconductor memory device comprises an array of memory cells including spare memory cells.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.